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   Technical Basis

 

The key asset is a state-of-the-art pilot line in a 1,000 m2 class-1 clean room with a 24 h / 7 days per week mode of operation.

 

The Toolset is capable for 0.13 µm technology on 200 mm wafers. Cycle times are typically 2 days per mask level. Processing times from tape-in to the shipment of diced chips are about 10 weeks, depending to some extent on the technology used.

 

Key equipment for processing and inline measurement in the pilot line includes:

• I-line and DUV (248 nm laser exposure) photolithography

• CMP in front-end of line (oxide, poly Si) and back-endof line (oxide, tungsten)

• Dry etch processes for standard CMOS and BiCMOS process modules

• PVD (Co, Al, Ti, TiN) and CVD (W, TiN) for the Al metallization system

• PECVD (inclusive HDP) and SACVD for deposition of dielectrics in front-end of line and

   back-end of line

• Wet etch and wet cleaning processes required for 0.13 µm technology level

• Low temperature Si, SiGe, SiGe:C epitaxy (differential, and selective epitaxy)

• Standard high temperature Si epitaxy

• Low to medium energy and low to high dose ion implantation

   (As, B, P, In, Sb, Si, Ge, F, Ar)

• Oxidation, LPCVD (including low temperature oxide and nitride), and annealing in

   standard batch systems

• RTP for annealing, oxidation, and silicidation

• Inline measurements for CD, overlay, thickness, resistance, defectivity, topology

   (SEM,  AFM), and XRD

• Parametric test using two fully automatic test systems

 

The following key methods are employed for offline diagnostics and analytics, electrical measurements, and reliability tests:

• SIMS, TEM, SEM, AES, XRD, XRR, XPS, AFM, and FTIR

• DC Parameter set-up for on-wafer and packaged device measurements

• LF Noise setup for 1/f noise on wafer measurements

• Ring oscillator set-up for on-wafer and packaged device measurements

• S-Parameter/DC/RF-noise equipment for on-wafer measurement

• S-Parameter/DC equipment for parameter extraction, device modeling

• Digital tester for digital/mixed signal functional test

• MOS-CV/IV equipment for DC/CV characterization

• Load Pull system

• Universal Microwave setup

• Tester for intrinsic reliability tests for technology qualification




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09-02-10
EU project DOTFIVE presents circuits operating up to 650GHz at ISSCC in San Francisco, USA on February 11, 2010 (International Solid-State Circuits Conference).
The chips were designed at University of Wuppertal and fabricated using IHP SiGe technology with highest HBT performance developed within the frame of the project.
[more]


09-10-09
2009 IEEE International Electron Devices Meeting (IEDM)
Hilton Baltimore
Baltimore, MD
December 7 - 9, 2009 [more]


22-06-09
8th Workshop
High-Performance SiGe:C BiCMOS (September 16, 2009) and Tutorial IHP Design Kits (September 17-18, 2009)

[more]


07-04-09
LFoundry and IHP sign cooperation contract
LFoundry to license IHP’s world leading LDMOS process module [more]


[more news]