Design-for-Testability

Design-for-Testability is an internal project serving two main purposes:

• Establish and operate test infrastructure and provide functional test services for internal design projects, technology qualification and yield control and, on request, for external customers.
• Conduct research in the area of "Design for Testability".

Advances in technology allow the design and fabrication of increasingly complex devices, consisting of multiple processor cores, ASIC blocks, memory, analog circuitry, etc. Much of this complex functionality is not directly accessible from outside any more and thus cannot easily be tested using traditional test technologies. In this project we investigate new and improved mechanisms and schemes to allow the debugging and testing of current and future complex devices. One special focus is the test of asynchronous circuits.

Having in-house test capabilities available allows tight integration and close cooperation between design, technology and test teams. Results from the research part of the project can also be evaluated in practice.

The project is founded by IHP.

Hardware

• Verigy 93000 SOC Pinscale production test system, 256 digital channels up to max 400 MHz, 32 channels up to 1.8 Gb/s datarate
• Accretech UF200 fully automatic wafer prober, temperature controlled chuck (-25°C - +125°C); attachable to the Verigy 93000 test system
• Teseda V520 structural tester
• Two Advantest CertiMAX debugging test systems, 256 digital channels up to 125 MHz
• Accretech UF200 fully automatic wafer prober, attached to one of the debugging test systems

Additional Software

• TSSI TDS commercial softare package for test pattern conversion and vector generation
• Several self-developed tools for test protocol generation and data extraction and analysis