TAMPRES

TAMper Resistant Sensor node

Design of a tamper resistant sensor nodes = resistance against physical attacks. ==> Improved trustworthiness OF THE FUTURE INTERNET OF THINGS due to protection of weakest link, I.E. THE SENSOR NODES.

• Prevention of side-channel and fault-injection attacks: evaluation and development of appropriate counter measures considering the severe constraints of energy and silicon area.
• Provision of flawless implementation of lightweight cryptographic cores: development of secure and properly implemented light-weight crypto cores to provide uncompromised cryptographic strength to higher layers.
• Attack resistant system architecture: secure integration and partitioning of the whole system including hardware components and secure low level services.

• Project Coordination
• Crypto cores and trusted sensor node
• Protection of debug and test interfaces (scan chain, JTAG)
• System Design and integration of components
• Manufacturing of test circuits, measurement and validation of protection ideas

The project is funded by EU FP7 (258754).