Gigabit WLAN

60 GHz sliding IF transmitter

Transmitter chip with:

• Complete PLL with 12 GHz IF output and 48 GHz RF output
• I/Q-Modulator to 12 GHz IF
• Up converter from 12 GHz IF to 60 GHz RF
• Power amplifier with Psat ~ 15 dBm
• SPI-interface

60 GHz sliding IF receiver

Receiver chip with:

• Complete PLL with 12 GHz IF output and 48 GHz RF output
• I/Q-Demodulator from 12 GHz IF to baseband
• Down converter from 60 GHz RF to 12 GHz IF
• LNA and VGA
• SPI-interface

60 GHz beamforming receiver chip

Eight channel 60 GHz beamforming receiver

• Size: 2.9 x 4.2 mm²
• Power dissipation: 1.2 W
• 1dB compression point: IF OP1dB = -3 dBm,  RF IP1dB = -25 dBm
• Phase control using RF Vector modulator: more than 25 dB amplitude control, 360º phase control

Architecture of 60 GHz OFDM Baseband Transmitter

For the development of the 60 GHz OFDM baseband processor, first a complete MATLAB model was developed. The simulation of different realizations of the wireless channel is the basis for the parameter optimization. Subsequently the MATLAB model was converted into a VHDL code and implemented on a high-performance FPGA platform. The block diagram shows the structure of the developed baseband transmitter. A 32-bit-wide data bus with a clock frequency of 125 MHz is used to stream data from the MAC. After buffering und scrambling, data is passed to the Reed Solomon encoder or a second buffer stage, which synchronizes the data to the 200 MHz clock domain. The same buffer is used for the signal field, which is generated in parallel and not RS-encoded. The next module is the convolutional coder. To reach the maximum throughput of 4 Gbps, data is processed with up to 24 parallel encoding streams. This is due to the implemented Viterbi decoder, which operates at a clock frequency of 200 MHz, providing a data throughput of 200 Mbps per stream. The system uses a single memory-based block interleaver, providing a throughput of 6.4 Gbps with 200 MHz clocking. Up to here, the data interfaces between the modules are always 32-bit wide. After interleaving, the data is reformatted to form 8 streams with 1-4 bit depending on the modulation scheme. Eight parallel mappers are used. Within the pilot insertion stage, mapped data symbols are transferred to the 270 MHz clock domain. A cyclic prefix is added by the IFFT module and the computed OFDM symbol is output to the DACs. The preamble is pre-calculated during implementation time and stored in a memory. This is accessible from MAC-layer through a memory-mapped interface and therefore configurable.

Architecture of 60 GHz OFDM Baseband Receiver

The receiver consists of two main parts, a digital front-stage and a data-path processing unit. The structure of the latter is shown in block diagram. An Analog-to-Digital converter samples the baseband signal from the analog front end at 2.3 Gsamples/s with 8 bit resolution for I and Q. This is the input to the digital front-stage, which performs synchronization and channel estimation. It also removes the zero and pilot carriers as well as the cyclic prefix . Finally, the frame data are transferred with 8 parallel streams at 200 MHz to the data path receiver unit. There, the data flow is the reverse of the transmitter. First, symbols are demapped and weighted with calculated power vectors. A resolution of 5 soft-bits is used for further processing. Just like the interleaver, a single de-interleaver is used. The de-interleaver is followed by the channel decoding. Up to 24 Viterbi decoders are used. The first stream additionally implements the signal field decoding. Depending on the use of Reed-Solomon-encoding, Viterbi-decoded bits are passed to the RS-decoding unit or a buffer stage, which synchronizes the data stream to 125 MHz. Finally, data is descrambled and delivered to the MAC layer.

High Performance Multi-Gbit MAC Processor

Guarantees data delivery on an unreliable channel

The transmission of data over our 60 GHz OFDM system needs a controller that manages the access to the wireless medium and performs an ARQ protocol to guarantee data delivery on an unreliable channel. It connects to the environment via a standard Gigabit Ethernet, which allows easy integration into existing network systems without writing drivers for different host operating systems. An integrated UDP stack enables the configuration and the monitoring of the system. The MAC processor is implemented fully in hardware in a Xilinx Virtex5 FPGA. A physical data rate of 4 Gbps is reached with the internal 32-bit data path structure and 125 MHz system clock. So it will match the capabilities of our OFDM baseband processor. The block diagram shows an overview of the MAC system.

Localization Techniques

Concept of distance measurement based on round trip delay

We have developed a localization method for OFDM networks based on the measurement of the Round trip Time of Flight (RToF) between pairs of terminals. For the 60 GHz and 5 GHz bands we have built demonstrators to verify the concept and to measure the performance (Fig 1). They use standard OFDM WLAN frontends (IEEE 802.11a / ad) with only slight modifications in the physical layer. The achievable accuracy is below 1 cm at 60 GHz and below 1 m at 5 GHz, if directional antennas are used. It can be further enhanced by using multiple measurements, prediction and filters (e.g. Kalman filter).