Design & Test Methodology

• Test Methodologies
• Embedded Test-Processors
• GALS & Asynchronous Systems
• Radiation Hard Design
• Dependable Design

• Design and test of digital SoCs
• PCB design

Main focus on development of GALS technology for better system integration, EMI reduction, and low-power. Our activities are supported with more then 10 year experience in the field and involvement in various projects: ASPIDA (FP5), GALAXY (FP7- IHP Coordinator), SUCCESS (FP/ - IHP Coordinator), GAELS (ESPRC - IHP external collaborator).  

Main achievements are CAD tool development for EMI estimation for GALS and synchronous systems, new GALS methods based on pausible clocking, EMI reduction methodology based on GALS, practical demonstration in various systems: GALS WLAN baseband processor (0.25 um CMOS), GALS/SYNC FFT processor (0.13 um CMOS), Moonrake - Gigabit OFDM Transmitter (40 nm CMOS), Lighthouse - Integrated GALS radar module (130 nm CMOS).

Fig. 1: CAD tool for high level EMI modeling of synchronous and GALS

Fig. 2: Low-EMI FFT processor developed to evaluate low-EMI GALS techniques and modeling software

Main highlight of our GALS activities is Moonrake chip, GALS and synchronous OFDM gigabit transmitter for 60 GHz band. This is 16M equivalent gates (9mm2) chip produced in 2010 in TSMC 40-nm CMOS process. With IHP-special GALS methodology we have achieved area reduction of 4.7%, power reduction of 8.2%, and EMI reduction up to 26 dB in comparison to the corresponding synchronous processing unit.

Fig. 3: Moonrake Chip

 Main focus on development of Radiation hard circuits, corresponding design flow and methods for fault tolerant and dependable computing. Our activities include the involvement in various projects: Middleware Switch ASIC (DLR), VHiSSi (FP7) and ZUSYS Graduate School in collaboration with BTU Cottbus.  

Main achievements are development of the complex Middleware Switch ASIC (0.25 um CMOS) and development of innovative selective fault tolerant methodology. Furthermore, we are now developing solutions for fault tolerant flexible multi-.core architecture, new methods for error detection and correction in non-volatile memories, implementation of very high speed serial interface. This work is enabled by existing radhard library for 0.25 um process with ongoing evaluation of the project for radiation hard applications. The similar process has been started also for our 0.13 um CMOS technology.

Main highlight of our dependable activities is Middleware Switch chip implementation. MW switch represents the key part of a SCAN (Spacecraft Area Network) system. This is a crossbar switch for 6 simultaneously high speed channels @ 50 Mbit/s, with 16 additional DMA channels for low speed devices (RS-232, RS-422, RS-485). It supports broadcast/ Multicast/ Point-to-Point (subscriber transmissions model). This ASIC is implemented in 0.25 um CMOS process with the complexity of 64mm2 and maximum frequency 100 MHz.

Fig. 4: Middleware Switch Processor

Main focus is research on advanced test methods for digital circuits, in particular for asynchronous and GALS designs. Mainly the methods bas based is test processor approach. Our activities have been in the background of many funded project and supported by DEDIS Graduate School in collaboration with BTU Cottbus..  

Main achievements is development of the test processor enabling timing deterministic test of asynchronous systems and test monitoring circuits for handshake components. Furthermore, coupled with our test service that we provide, based on Agilent 93k ATE and Certimax test device, we are working on advanced solutions extending use of industry related ATE equipment,

Main highlight of our test activities is development of Test processor for deterministic testing of asynchronous systems. The main goal was to extend the standard ATE infrastructure with an additional test processor enabling the test of non-deterministic designs such as even driven asynchronous logic. This design is developed in LISAtek tool and co-integrated in respect to test flow with actual test infrastructure based on Agilent 93k tester.

Fig. 5: Test processore architecture