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Design & Test Methodology

Main Fields

     

  • Fault tolerant and Radiation Hard Design Methods

    • Adaptive methods for fault tolerant design

  • Novel design methodologies

    • asynchronous and GALS design
    • low-power design methods
    • high-speed differential design

  • Design for Testability and Test Methodology
  • Applied wireless communication system design for space and traffic applications

    • Satellite communication systems
    • TPMS sensors for traffic management

  •  

Service

     

  • ASIC Design
  • Test of digital and mixed-signal SoCs
  • PCB desig
  •  

Fault tolerant and Radiation Hard Design Methods

Main focus on development of Radiation hard circuits and ASICs, corresponding design flow and methods for fault tolerant and dependable computing. Our activities include the involvement in various prior and ongoing projects: Middleware Switch ASIC (DLR, finished), VHiSSi (FP7, finished) and ZUSYS Graduate School (finished with 2 PhD dissertations). RTU ASIC Development project (industry, ongoing), Different (FP7, ongoing), Chirp IC (MP, ongoing), MOTARO (DFG over BTU-CS, ongoing), SEPHY (H2020, will start in 2015), LIBRA (EUROSTARS, will start in 2015).

 

Main achievements are developments of adaptive fault tolerant multi-core processing platform and corresponding FMP ASIC (0.13 um CMOS), and complex Middleware Switch ASIC (0.25 um CMOS). Furthermore the advanced methods for dependable non-volatile memory control of innovative selective fault tolerant methodology have been performed. IHP has also contributed to the successful EU project VHiSSi which has delivered SpaceFibre switch ASIC for space applications in 130 nm technology, achieving serial link throughput of 3.25 Gbps, Finally, the basic methodology for protection of pipelined circuits against soft errors has been elaborated and also methodology for system level latch-up protection has been proposed. This work is aligned with the development of the radhard design flow and digital libraries for 0.25 um and 0.13 um, where the main focus is paid to the specially design TMR flip-flops and fully developed methodology for their use in standard design flow. Those activities are also incorporated into ongoing evaluation of the IHP technology for radiation hard applications.

 

Main highlights are the following:

The concept for adaptive fault tolerant multi-core computing platform has been developed. For increasing the lifetime of the multi-processor a special youngest-first scheduling methodology has been proposed. It has been demonstrated that in comparison with the state-of-the-art methods this methodology could increase the system lifetime up to 31%. To verify the concept the complex 8-core processor FMP chip has been produced in 130 nm process and successfully tested.

 

Middleware Switch chip implementation is also an important highlight of our activities. MW switch represents the key part of a SCAN (Spacecraft Area Network) system. This is a crossbar switch for 6 simultaneously high speed channels @ 50 Mbit/s, with 16 additional DMA channels for low speed devices (RS-232, RS-422, RS-485). It supports broadcast/ Multicast/ Point-to-Point (subscriber transmissions model). This ASIC is implemented in 0.25 um CMOS process with the complexity of 64 mm2 and maximum frequency 100 MHz.

Fig. 1: Block diagram of the adaptive fault tolerant multi core processing framework

Fig. 2: Chip foto of the adaptive fault tolerant multi core processing framework

Novel Design Methodologies

Fig. 3: CAD design flow and CAD tool for design preconditioning and switching noise evaluation

Main focus on development of asynchronous and GALS technology for better system integration, design technologies for EMI and substrate noise reduction, low-power design methods and high speed differential design. Our activities are supported with more than 10 year experience in the field and involvement in various finished projects: ASPIDA (FP5), GALAXY (FP, IHP as Coordinator), SUCCESS (FP7, IHP as Coordinator), GAELS (ESPRC, IHP as external collaborator), IC-NAO (EUROSTARS) and in the ongoing project GASEBO (DFG by BTU-CS).

 

Main achievements are CAD tool for switching noise evaluation, design pre-conditioning and estimation for GALS and synchronous systems, new GALS methods based on pausible clocking, EMI and substrate noise reduction methodology based on GALS, practical demonstration in various systems: Moonrake - Gigabit OFDM Transmitter (40 nm CMOS), Lighthouse - Integrated GALS radar module (130 nm CMOS), low-noise test ASIC which is functionally a trusted sensor node, named SCREAMER (130 nm).

 

Main highlight of our GALS activities is Moonrake chip, GALS and synchronous OFDM gigabit transmitter for 60 GHz band. This is 16M equivalent gates (9 mm2) chip produced in 2010 in TSMC 40-nm CMOS process. With IHP-special GALS methodology we have achieved area reduction of 4.7%, power reduction of 8.2%, and EMI reduction up to 26 dB in comparison to the corresponding synchronous processing unit.

Fig. 4: Moonrake Chip foto and its respective results

Fig. 5: Measured advantages of GALS design

Design for Testability and Test Methodologies

Fig. 6: Block diagram of NoTePAD test processor

Main focus is on the development of a concept for functionally testing of asynchronous circuits to increase testability and to enable debugging of such designs. Asynchronous and GALS design techniques are one of the activities pursued by our group for many years. With our test concept, we intend to strongly contribute to establishing asynchronous design as a key technology for future integrated circuits.

 

Main achievement is a complete framework implementing the concept for functional tests of asynchronous designs. This includes a test processor solution called NoTePAD which provides generic interfaces for asynchronous handshake circuits. Besides this, a workflow and a tool chain to obtain test processor programs implementing the functional tests of a given asynchronous design have been developed. Thereby, the complete workflow is based on standard functional simulation of the design with common commercial tools. Furthermore, a special test pattern format for describing the timing elastic test sequences has been developed.

 

Main highlight is the developed test processor concept and its NoTePAD realization as such. It is a breakthrough in asynchronous circuit testing as it is a highly flexible functional testing and debugging platform, which has not been available before.

Selected publications

1. V. Petrovic , G. Schoof, Z. Stamenkovic, “Fault-tolerant TMR and DMR circuits with latchup protection switches”, Journal Paper - Microelectronics Reliability, Volume 54, Issue 8, Pages 1613-1626, August 2014 Elsevier Ltd.

2. M. Krstic, X. Fan, E. Grass, L. Benini, M. R. Kakoee, C. Heer, B. Sanders, A. Strano, D. Bertozzi, Evaluation of GALS Methods in scaled CMOS Technology – Moonrake Chip Experience, International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 2012, Vol. 3. Iss.4, pp 1-18, DOI: 10.4018/jertcs.2012100101

3. M. Krstić, T. Krol, X. Fan, E. Grass, Reducing EMI using GALS Approach, Journal of Low-Power Electronics, JOLPE - Vol. 6, N° 1, April 2010 - Special Section on PATMOS'09, American Scientific Publishers, Volume 6, Number 1, April 2010, pp. 181-191(11).

4. M. Krstić, E. Grass, F. Gürkaynak, P. Vivet, Globally Asynchronous, Locally Synchronous Circuits: Overview & Outlook, IEEE Design & Test of Computers, Vol. 24, No. 5. September-October 2007, pp. 430-441.

5. V. Petrovic, G. Schoof, M. Krstic, Verbesserter TMR-Strahlungsschutz für ASIC-Layouts, 27. Gesellschaft für Informatik / VDE/VDI-Gesellschaft Mikroelektronik, Mikrosystem- und Feinwerktechnik / Informationstechnische Gesellschaft im VDE – Workshop, Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2015).

6. N. Savic, M. Junghans, M. Krstic, Evaluating Tire Pressure Monitoring System for Traffic Management Purposes – Simulation study, 17th International IEEE Conference on Intelligent Transportation Systems - ITSC 2014, Qingdao, China, October 8-11, 2014.

7. O. Schrape, M. Appel, F. Winkler, M. Krstic, Low-Power Design Methodology for CML and ECL Circuits, 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2014), Palma de Mallorca, Spain.

8. A. Simevski, R. Kraemer, M. Krstic, Investigating core-level N-modular redundancy in multiprocessors, 8th IEEE 8th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-14) September 23-25, 2014, Aizu-Wakamatsu, Japan.

9. A. Simevski, R. Kraemer; M. Krstic, Increasing multiprocessor lifetime by Youngest-First Round-Robin core gating patterns, NASA/ESA Adaptive Hardware and Systems conference (AHS-2014), Leicester, 2014.

10. M. Krstic, S. Weidling, V. Petrovic, M. Gössel, Improved Circuitry for Soft Error Correction in Combinational Logic in Pipelined Designs, IEEE International On-Line Testing Symposium 2014.

11. S. Zeidler, M. Goderbauer, M. Krstic, Design of a Low-Power Asynchronous Elliptic Curve Cryptography Coprocessor, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Abu Dhabi, UAE, Dec, 2013.

12. A. Simevski, R. Kraemer; M. Krstic, Automated Integration of Fault Injection into the ASIC Design Flow, 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2013), New York, USA.

13. X. Fan, O. Schrape, M. Marinkovic, P. Dähnert, M. Krstic, E. Grass, Optimal GALS Design for Spectral Peak Attenuation on Digital Switching Current, IEEE ASYNC 2013, Santa Monica, USA.

14. S. Zeidler, C. Wolf, M. Krstic, R. Kraemer, Functional Pattern Generation for Asynchronous Designs in a Test Processor Environment, IEEE Asian Test Symposium 2012.

15. A. Simevski, E. Hadzieva, R. Kraemer, M. Krstic, Scalable Design of a Programmable NMR Voter with Inputs’ State Descriptor and Self-checking capability, 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2012).

16. X. Fan, M. Krstic, E. Grass, Performance analysis of GALS datalink based on pausible clocking scheme, IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) 2012.

17. X. Fan, M. Krstić, E. Grass, B. Sanders, C. Heer, Exploring Pausible Clocking Based GALS Design for 40-nm System Integration, DATE 2012.

18. X. Fan, M. Krstic, C. Wolf, E. Grass, GALS Design for On-Chip Ground Bounce Suppression, 17th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2011.

19. X. Fan, M. Krstic, T. Krol, C. Wolf, E. Grass, A GALS FFT Processor with Clock Modulation for Low-EMI Applications, In Proc. ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors, July 7-9, 2010 Rennes, France.

20. X. Fan, M. Krstić, E. Grass, Analysis and Optimization of Pausible Clocking based GALS Design, In Proc. of XXVII IEEE International Conference on Computer Design (ICCD) 2009, Resort at Squaw Creek, Lake Tahoe, California, pp 358-365, "Best Paper" award.

Contact

Prof. Dr. Milos Krstic

 

IHP

Im Technologiepark 25

15236 Frankfurt (Oder)

Germany

Phone: +49 335 5625 729

Projects

Design-for-Testability

Research to make designs testable

DIFFERENT

DIgital beam Forming For low-cost multi-static spacE-boRnEsyNtheticaperTure radars

LIBRA

Development of a Rad-Hard Mixed-Signal Library for Commercialization of Space Qualified ICs

MPL

Modular Processor Library

SPAD

Development of a Space-Qualified Analog-to-Digital Converter

The building and the infrastructure of the IHP were funded by the European Regional Development Fund of the European Union, funds of the Federal Government and also funds of the Federal State of Brandenburg.