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High-k dielectrics for sub 0.1 µm MOSFET technologies


Development of alternative high-k dielectrics for future MOSFET technologies.


Figure 1 at the top shows the dimensions of the historical point contact transistor built at Bell laboratories by John Bardeen and Walter Brattain in Shockley`s group [1]. The point contact transistor consists of a piece of n-type Ge several mm in size on a metal plate which served as the gate contact and two springs loaded top contacts, called emitter and collector. Biasing the back contact produced an inversion layer in n-Ge on the top side and a hole current was observed between the emitter and the drain. Later on, Si became the semiconductor of choice for integrated circuits due to the higher interface quality of the SiO2 / Si boundary. Since 1955, when the first metal-oxide-semiconductor field-effect transistor (MOSFET) on Si was developed, its dimensions have been continuously reduced to enable higher speed and packing density of the silicon integrated circuits [2]. The bottom part of Fig. 1 shows a state-of-the art 10 nm research MOSFET prototype from Intel [3].

Particularly challenging in shrinking MOSFET device dimensions in the nanoscale regime is the fact that the SiO2 gate oxide thickness needs to be decreased to below 1 nm. In this thickness regime, direct tunneling becomes the dominant leakage mechanism, resulting in a rapid rise of the transistors stand-by power to a level which cannot be accepted. This is especially true for portable electronic devices [3]. Therefore, to reduce the power dissipation and enable further miniaturization, an alternative insulator of higher dielectric constant (high-k dielectric) must be integrated in the conventional planar MOSFET technology [4, 6].

Fig.1: Historical point contact transistor (left) [1] in comparison with a 10 nm research MOSFET [3] (from [5]).

The alternative high-k dielectric and its interface with silicon must satisfy a wide range of stringent demands. These can be best understood by regarding a modern planar MOSFET device at work, as shown in Fig. 2. The transistor switches from the off- to the on-state by applying a positive voltage to the gate electrode. The p-Si substrate underneath the insulating gate dielectric becomes inverted. Inversion means that the minority carriers of the wafer material, in our case electrons, become the dominant charge carriers in the Si surface region. In that way, a conducting n-channel is formed in the surface region of the p-Si wafer and a current flows from the source to the drain. The latter results because the drain electrode is held at a slightly more positive potential than the source, which is usually connected to ground.

Advanced high-k dielectric materials in future complementary metal-oxide-semiconductor (CMOS) transistor technologies will have to fulfill the following very challenging requirements [5, 6]:

1) equivalent oxide thickness (EOT) < 1 nm

2) gate leakage current advantage over the traditional SiO2 dielectrics

3) excellent reliability (time dependent dielectric breakthrough (TDDB) characteristics etc.)

4) good microprocessing capability and thermal stability

5) high mobility (electrically stable interface with few defects)


Research in our group is mainly focused on rare earth-based dielectrics with high ionic and electronic polarizabilities which contribute to relatively high dielectric constant values of these compounds [7]. Another family of dielectrics investigated at IHP are HfO2-based materials.

Fig. 2: Schematic view of a n-channel MOSFET in the on-state [5].

Screening of new dielectric materials for CMOS applications at IHP involves extensive physical and electrical characterization. The availability of MOSFET test structures from our cleanroom facilities is a special opportunity to study alternative gate dielectrics for CMOS applications at IHP.


The MOSFET test chips contain pre-prepared NMOS and PMOS transistor structures which, after removing a protective oxide layer (gate replacement approach), can be covered with high-k dielectric and metal gate electrode layers. After gate stack deposition, only one additional lithography step is required to obtain fully functional high-k/metal gate CMOS transistors [Fig. 3]. In this simple way, an advanced characterization of high-k gate dielectrics in MOSFET structures can be performed.

Fig. 3: IHP test structures enable easy and fast evaluation of various high-k dielectrics in MOSFET device.

Besides the structures for high-k/metal gate stack testing the test chip contains also conventional SiO2-based CMOS devices serving as references. The high-k MOSFET test structures are manufactured on 8-inch Si wafers in the IHP cleanroom facilities and are offered to project partners as well as to external customers.

Fig. 4:Fragment of the high-k test chip containing NMOS and PMOS transistors.

The building and the infrastructure of the IHP were funded by the European Regional Development Fund of the European Union, funds of the Federal Government and also funds of the Federal State of Brandenburg.